Ben Pouladian

On the flight back from GTC to Los Angeles last night I sat next to one of Micron’s senior cloud division sales leaders. He was headed to OFC — because when you’re the company supplying memory to every AI rack on the planet, the optical interconnect conference and the GPU conference happen in the same week of your life.

His framing was blunt: there’s been a decade of underinvestment in memory. All the capital flowed to ASICs — custom silicon, accelerators, GPUs — while the industry that feeds them starved. The result is a supply-demand imbalance that Wall Street models haven’t fully accounted for. And it could persist for years.

Hours later, Micron reported the numbers that prove it.

The Numbers

Fiscal Q2 revenue hit $23.9 billion — up 196% year-over-year and 75% sequentially. That sequential increase of $10.2 billion is the largest in the company’s history. Gross margins reached 75%, a company record, nearly doubling from a year ago. EPS came in at $12.20, up 682% year-over-year — crushing the $8.79 consensus by nearly 39%.

And the guide? Fiscal Q3 revenue of $33.5 billion at 81% gross margins with $19.15 EPS. To put that in context: Micron’s single-quarter revenue guidance now exceeds the company’s full-year revenue for every year through fiscal 2024.

This is what a structural supply-demand dislocation looks like in real-time.

Micron revenue by fiscal quarter. FQ3 guide exceeds every full-year revenue through FY2024.
Source: Micron earnings, BEP Research.

The Memory Wall, Validated

Regular readers know the framework. In The Memory Wall, I argued that AI inference is fundamentally memory-bound, not compute-bound. In The Memory Wars, I mapped how the 16-Hi HBM race and structural cleanroom constraints were reshaping competitive dynamics across the memory oligopoly. In The DRAM Squeeze, I showed how AI infrastructure’s insatiable appetite for bandwidth was crowding out consumer electronics — smartphones as the first casualty.

Tonight, Sanjay Mehrotra confirmed every thread of that thesis. On the call, he was emphatic: AI hasn’t just increased demand for memory — it has fundamentally recast memory as a defining strategic asset in the AI era.

That’s not a CEO describing a cyclical upturn. That’s a CEO describing a phase change.

The Supply Gap, Quantified

The most important exchange on the call came from Morgan Stanley’s Joseph Moore, who pressed Sanjay on allocation. Last quarter, Micron disclosed they were fulfilling only 50% to two-thirds of customer demand in the medium term. Moore asked if that had changed.

Sanjay’s answer: “Yes, that still remains the case.”

Let that sink in. The company just printed $23.9 billion in revenue and is guiding $33.5 billion — and they’re still only meeting half to two-thirds of what customers are asking for. The fabs being built today — Tongluo, Idaho, New York, Singapore — won’t produce wafers until 2027-2028. The gap between supply and demand isn’t closing anytime soon.

As I wrote in The Memory Wars: “New fabs won’t relieve constraints until 2027-2028 at the earliest.” That timeline hasn’t changed. If anything, the demand side has accelerated faster than the supply response.

The Numbers Through the BEP Lens

DRAM: $18.8 billion in revenue, up 207% year-over-year. Prices increased in the mid-60s percentage range sequentially — on mid-single-digit bit shipment growth. This is almost entirely a pricing story driven by structural scarcity. DRAM inventory days remain below 120 — historically tight.

NAND: $5.0 billion, up 169% year-over-year. Prices up in the high-70s percentage range. Data center NAND revenues more than doubled sequentially, driven by vector database and KV cache offload — the exact use cases I mapped in The Memory Wall when describing the tiered hierarchy: HBM for hot weights, SSD for cold context, with BlueField-4 managing lifecycle across the stack. Micron explicitly stated NAND demand is “significantly in excess of available supply for the foreseeable future.”

HBM4: Volume shipments of 36GB 12-High underway for NVIDIA’s Vera Rubin. The 16-High product sampled at 48GB per cube. HBM4E development targeting calendar 2027. At CES, I noted that “the 16-Hi HBM4 race just got more urgent — NVIDIA’s demand for 22 TB/s bandwidth per GPU means HBM4 capacity is the binding constraint.” Micron is executing on exactly that timeline.

The GTC Convergence: Groq LPX Validates the Fourth Piece

Barclays’ Tom O’Malley asked the question I was waiting for — directly referencing GTC and OFC conversations about the LPU architecture and SRAM. Sanjay’s response was the clearest validation of The Fourth Piece thesis I’ve seen from a memory vendor:

The Groq LPX rack uses 12 terabytes of DDR5 alongside Vera Rubin. It doesn’t replace HBM — it complements it. As Sanjay put it: architectures that make AI infrastructure more efficient are good for all AI because they help the pie grow faster. The LPU architecture works in conjunction with Vera Rubin, not instead of it.

This is exactly what I mapped in The Fourth Piece: Groq’s dataflow compiler and NVIDIA’s platform aren’t competing — they’re co-designed pieces of a rack-scale inference architecture that requires massive memory footprints across HBM, LP DRAM, DDR5, and SSD simultaneously. Every layer of Micron’s portfolio is seeing record demand because the architecture demands it.

The Margin Question: Structural or Cyclical?

Bank of America’s Vivek Arya pushed Mark Murphy on whether 81% gross margins can sustain — noting that Micron’s prior cyclical peak was in the low 60s. Murphy’s response was the most consequential language from a memory CFO in years.

His argument: AI is a transformational secular driver, not a cyclical blip. Memory is being recognized as far more valuable — an efficient way to monetize AI from data center to the edge. The supply constraints are structural: declining bits per wafer on node advances, increasing HBM trade ratios, and any new capacity requiring greenfield construction with multi-year lead times. Both the value proposition and the supply limitations are durable.

There was another critical data point buried in the C.J. Muse exchange: Sanjay confirmed that non-HBM margins are currently higher than HBM margins. That inverts the popular narrative that HBM is where all the pricing power lives. DDR5 and LP DRAM margins are above HBM — because conventional DRAM is even more supply-constrained than HBM in absolute terms. This is the underinvestment thesis that Micron’s cloud sales leader was describing on our flight.

The Consumer Squeeze Accelerates

Micron warned that PC and smartphone units could decline in the low-double-digits in calendar 2026, partially driven by DRAM and NAND supply constraints redirecting capacity toward AI infrastructure. The bifurcation I mapped in The DRAM Squeeze is no longer a theoretical risk — it’s showing up in Micron’s own guidance.

Smartphones shipping with 12GB+ of DRAM jumped from under 20% to nearly 80% in a single year. PCs with on-device agentic AI need 32GB minimum — twice the average. Personal AI workstations ship with 128GB. The content per device is exploding at the exact moment supply can’t keep up.

Strategic Customer Agreements: The Business Model Shift

Micron signed its first five-year Strategic Customer Agreement and is in discussions across multiple customers and multiple end markets. Sanjay wouldn’t name the customer or disclose specifics, citing confidentiality. But the signal matters: memory is transitioning from commodity spot transactions to multi-year strategic commitments with locked terms — the kind of relationship that semiconductors like GPUs and networking ASICs have enjoyed for years but memory never has.

Timothy Arcuri pressed on whether these SCAs provide gross margin floor protection on the downside. Sanjay wouldn’t confirm specifics but emphasized that the agreements have “robust terms” providing “visibility and stability toward our business model.” That’s as close to a floor mechanism as you’ll get from a CEO in a public call.

How Long Can This Last? Connecting the Dots

This is the question every investor is asking. So let’s triangulate.