AI and Investing Is the Future!
Intel Foundry’s advanced packaging technology is emerging as a genuine alternative to TSMC’s capacity-constrained CoWoS—but the reported customer wins require careful scrutiny, and Intel’s execution track record warrants significant skepticism.
The core thesis has merit: hyperscalers desperately need packaging capacity that TSMC cannot provide, and Intel’s EMIB offers a technically sound solution with available US-based capacity. However, this is a 2027+ story with substantial execution risk, not an imminent catalyst.
Of the five claimed EMIB customers, only NVIDIA’s partnership is confirmed. Google TPU adoption appears likely but targets v9 (2027), not v8 as some reports claimed. AWS Trainium evidence is nonexistent. Apple engagement appears exploratory at best. The investment opportunity exists, but investors should understand they’re betting on Intel executing multiple first-of-kind technologies simultaneously—something the company has failed to do consistently in recent years.
Advanced packaging has become the critical bottleneck in AI hardware production. I’ve written previously about how CoWoS capacity, not transistor density, determines who wins in AI semiconductors. In that analysis, I detailed how NVIDIA commands an estimated 70%+ of TSMC’s CoWoS-L allocation, with Broadcom’s hyperscaler empire—serving Google, Apple, Meta, Anthropic, OpenAI, and ByteDance—capturing most of the remainder. The Blackwell delays in Q3-Q4 2024 stemmed directly from CoWoS-L yield issues related to CTE (coefficient of thermal expansion) mismatch—a preview of the packaging challenges that intensify as chip complexity grows.
Modern AI accelerators like NVIDIA’s Blackwell or Google’s TPUs aren’t single monolithic chips—they’re multiple smaller chips (called “chiplets”) that must communicate at extremely high speeds. The packaging technology that connects these chiplets determines system performance as much as the transistors themselves.
Think of it like lasagna. CoWoS is traditional lasagna—large continuous sheets of silicon (the pasta) spanning the entire package, with everything layered on top. The interposer connects all the chip dies, but those big silicon sheets are expensive, prone to warping at scale, and trap heat underneath. EMIB is more like a deconstructed version: small silicon bridges only where dies actually need to connect, with the chips sitting directly on the substrate. Less elegant perhaps, but it scales bigger, runs cooler, and costs less.
Intel introduced EMIB in 2017 and has shipped over a million units in products including Stratix FPGAs, Sapphire Rapids server CPUs, and the Ponte Vecchio GPU. The technology works. What’s new is hyperscaler interest driven by CoWoS capacity constraints—demand for advanced packaging now exceeds TSMC’s supply by nearly 3x, with NVIDIA alone consuming 60% of available CoWoS capacity through 2027.
Intel is building substantial packaging capacity to meet this demand. Project Pelican in Malaysia represents a $7 billion, 710,000 square foot advanced packaging facility—slightly smaller than TSMC’s AP8 but purpose-built for EMIB and Foveros. Combined with the $3.5 billion Fab 9 in New Mexico (Intel’s current packaging hub where almost all Intel products are packaged today) and Arizona’s advanced packaging R&D center, Intel is positioning for serious scale. As Alex_Intel_ notes in his detailed fab analysis, “Intel’s EMIB solution is also more efficient given it does not need to waste silicon on wafers. Instead, it is a silicon bridge.”
The efficiency advantage is quantifiable: Intel’s own data shows EMIB achieves 90% wafer utilization compared to just 60% for traditional silicon interposers like CoWoS. The math is straightforward—small bridges pack efficiently on a wafer with minimal edge waste, while large reticle-sized interposers leave 40% of silicon on the cutting room floor. At scale, this 30% utilization advantage translates directly to lower cost per package.
EMIB’s key technical advantages include approximately 47% better power efficiency (0.30 pJ/bit vs 0.56 pJ/bit for CoWoS), superior thermal performance because local bridges don’t obstruct heat dissipation, and the ability to build significantly larger packages—up to 8-12x reticle size by 2027 versus CoWoS-S’s ~3.3x limit, according to TrendForce. Intel’s cost structure is also lower because EMIB avoids the expensive silicon interposers that represent 50-70% of CoWoS cost.
However, CoWoS remains technically superior for the highest-bandwidth applications. NVIDIA and AMD’s flagship GPUs will continue using CoWoS for its lower latency and higher interconnect density. EMIB’s sweet spot is custom ASICs, inference chips, and customers who need large packages but can tolerate slightly lower interconnect performance—exactly the profile of hyperscaler custom silicon.
The claimed customer list requires significant correction. Here’s what the evidence actually shows:
NVIDIA: CONFIRMED AND EXPANDING
In September 2025, NVIDIA announced a $5 billion investment in Intel, with CEO Jensen Huang explicitly citing packaging: “Intel has the Foveros multi-technology packaging capability… it’s really enabling.” The deal was finalized December 29, 2025, following FTC approval. Intel will provide advanced packaging for co-developed SoCs and CPUs for NVLink AI racks, with products expected late 2027 or early 2028.
Breaking (January 27, 2026): DigiTimes reports NVIDIA is exploring Intel collaboration for its next-generation Feynman GPUs. While the GPU compute die will remain at TSMC, the I/O die could be partially produced on Intel’s 18A or 14A process (targeted for 2028 mass production). Critically, advanced packaging is expected to use Intel’s EMIB platform, with the split estimated at up to ~25% Intel / ~75% TSMC. This would represent NVIDIA’s first significant use of non-TSMC packaging for flagship GPUs—a major validation of Intel’s EMIB technology. Final decisions depend on Intel 14A yield and ramp status.
Critically, NVIDIA’s current GPU line (Blackwell, Rubin) continues on TSMC CoWoS—the Feynman collaboration represents diversification, not displacement.
Google TPU: LIKELY, timeline disputed
TrendForce’s November 2025 report states “Google plans to implement EMIB in its 2027 TPU v9.” Current TPUs (v6 Trillium, v7 Ironwood) use TSMC CoWoS through Broadcom. However, FundaAI’s Q4 2025 analysis references “confirmed orders for Google TPU v8e,” suggesting EMIB adoption may come earlier than TrendForce indicated. The discrepancy likely reflects different TPU variants or timeline updates—regardless, Google engagement with Intel packaging appears substantive.
Meta MTIA: POSSIBLE, under consideration
TrendForce reports Meta “considers” EMIB for MTIA accelerators, but current MTIA (v1-v3) uses TSMC packaging with Amkor and Broadcom partnership. Meta has secured 50,000 CoWoS wafers for MTIA v3 in 2026. EMIB consideration is real but not committed.
Apple: UNCONFIRMED but increasingly substantive
Initial evidence consisted of job postings and analyst Ming-Chi Kuo reporting Apple received Intel’s 18A PDK. However, DigiTimes’ January 28, 2026 report provides significant new detail: Apple is reportedly negotiating with Intel to manufacture “entry-level M-series processors” for MacBooks—products currently fabricated at TSMC. This would represent Apple’s return to Intel manufacturing after departing in 2020 (Intel previously had a dedicated “Apple Group” production line at Oregon from 2005-2020, until 10nm delays contributed to Apple’s shift to Apple Silicon).
The motivation mirrors NVIDIA’s: satisfy Trump administration US manufacturing pressure while minimizing risk. Apple’s reported strategy is “small volume, low-end, non-core”—keeping flagship chips at TSMC while giving Intel lower-risk products. DigiTimes also reports Google, Microsoft, AWS, Qualcomm, Broadcom, AMD, and Tesla are all in various stages of discussion with Intel. No confirmed timelines, but 14A (2028) appears to be the consensus target node across these engagements.
AWS Trainium 4: NO CREDIBLE EVIDENCE
Despite extensive searching, I found no credible sources confirming AWS/Annapurna Labs is using Intel EMIB for Trainium. Current Trainium chips (2, 3) use TSMC 3nm with CoWoS packaging through Alchip. AWS has confirmed intent to use TSMC Arizona for supply chain diversification—not Intel.
The more consequential story isn’t packaging alone—it’s Intel’s strategy to bundle 14A process technology with EMIB as a complete “systems foundry” solution.
Having worked on silicon photonics and with EUV light source technology during my time at UC San Diego and Cymer, I’ve developed an appreciation for how difficult each successive node becomes. Intel 14A represents a genuine technological leap: second-generation RibbonFET (gate-all-around transistors), second-generation backside power delivery (PowerDirect), and the industry’s first commercial High-NA EUV deployment.
Intel claims 14A delivers 15-20% performance-per-watt improvement over 18A with 1.3x higher chip density. The company has completed acceptance testing of ASML’s EXE:5200B High-NA tool—the first production High-NA system globally. TSMC has explicitly stated it will not use High-NA EUV for its A14 or A16 nodes, believing low-NA multi-patterning is more cost-effective.
Timeline assessment: Intel targets 2027 risk production and 2028 high-volume manufacturing for 14A. This is achievable but aggressive. The key dependency is 18A proving viable first—and on that front, Intel just delivered a critical milestone.
In its Q4 2025 earnings released January 22, 2026, Intel confirmed 18A is now in production. CEO Lip-Bu Tan stated: “The introduction of our first products on Intel 18A—the most advanced process technology developed and manufactured in the United States—marks an important milestone, and we’re working aggressively to grow supply to meet strong customer demand.” CFO David Zinsner added that Intel “exceeded Q4 expectations across revenue, gross margin, and EPS even as we navigated industry-wide supply shortages,” noting that “available supply will be at its lowest level in Q1 before improving in Q2 and beyond.” This supply constraint narrative directly validates the thesis that hyperscalers need packaging alternatives like EMIB.
On the earnings call, Zinsner called out advanced packaging as the “brightest spot” for Intel Foundry, with several external engagements crossing from “hundreds of millions” into the billions of dollars. While not yet enough to push IFS into profitability, these deals lay groundwork for expanding relationships—the “land and expand” strategy where packaging gets Intel in the door for potential logic foundry upsells. Lip-Bu Tan indicated that 18A yields are currently around 60% with incremental ~7% monthly improvements expected, though the team cautioned this may not immediately flow to the bottom line given product mix. Intel was running approximately 40,000 18A wafers per month at year-end 2025, with goals to reach 100,000 wafers per month by end of 2026—a significant vertical scaling challenge alongside the horizontal customer expansion.
Notably, Tan and Zinsner confirmed they will not ramp 14A CapEx until external customer commitments are secured for wafer fabrication. This capital discipline signals both prudence and the reality that Intel Foundry’s future hinges on converting interest into binding orders.
The bundled offering Intel showcased at Foundry Direct Connect 2025 is ambitious: 16 compute tiles on 14A, up to 24 HBM sites, 48 LPDDR5X controllers, and greater than 12x reticle scalability. For hyperscalers building massive AI accelerators, this integrated solution—US-based leading-edge logic plus advanced packaging under one roof—addresses both supply chain diversification and technical requirements.
Customer interest appears real. Apple reportedly received the 18A-P PDK v0.9.1. NVIDIA is exploring 14A after pausing 18A testing. AMD has “high likelihood” of engagement per analyst reports. Microsoft and Amazon have confirmed 18A commitments. Intel’s internal view, per Reuters: “Intel sees 14A as more competitive than TSMC’s forthcoming offerings.”
Intel Foundry Services cannot yet be trusted to execute at scale for external customers—full stop. Despite confirming customer wins, Intel has never successfully manufactured chips for external customers at volume. MediaTek’s Intel 16nm chip is the first external foundry product going into production. The Microsoft and Amazon 18A deals are future commitments, not current revenue.
The yield situation has improved materially. Early 2025 reports from analyst Ming-Chi Kuo indicated 18A yields at just 20-30%, significantly below TSMC’s 60%+ at N2. On the Q4 2025 earnings call, Lip-Bu Tan confirmed yields have reached approximately 60% with ~7% monthly improvement expected going forward—a dramatic turnaround that validates the process technology even if margin benefits remain uncertain given product mix. This yield trajectory significantly de-risks Panther Lake (Core Ultra 3) production economics and strengthens the case for external foundry customers.
Financial losses are staggering: Intel Foundry lost approximately $13 billion in operating losses in 2024 on roughly $7 billion in operating expenses. Q3 2025 alone showed a $2.3 billion operating loss on $4.2 billion revenue. The business is hemorrhaging cash.
Beyond yield challenges, Intel faces a persistent shortage of substrates required for EMIB packaging, which could constrain near-term ramp even with strong customer demand. This substrate bottleneck affects the entire advanced packaging industry but is particularly acute for Intel as it attempts to scale external foundry business simultaneously with internal product needs.
Leadership turbulence adds uncertainty. Pat Gelsinger was forced out in December 2024 after the board lost confidence in turnaround pace. New CEO Lip-Bu Tan (former Cadence CEO) brings discipline and industry credibility but has explicitly warned Intel will “cancel 14A and beyond if no major external customer” emerges. The 40% workforce reduction since 2022—from 131,900 to target ~75,000 employees—raises execution capacity questions.
CHIPS Act funding provides critical support: Intel secured $7.86 billion in direct funding plus a $3 billion Secure Enclave defense contract. The government took a ~10% equity stake in August 2025, injecting $5.7 billion. This reduces existential risk but represents government subsidization of losses rather than commercial viability.
The comparison to Samsung Foundry’s struggles is instructive. Samsung faces 3nm yields below 20%, lost Google’s Tensor G5 to TSMC, and cancelled its $17 billion Taylor, Texas fab due to lack of customers. Intel faces similar yield challenges but has stronger government backing and more diversified business lines.
The diversification imperative is real, even if Intel’s specific customer wins require verification. As I detailed in The Packaging Paradox, the CoWoS capacity crunch has created a structural chokepoint constraining the entire AI hardware ecosystem. Four structural factors drive hyperscaler interest in alternatives:
CoWoS capacity crunch: Global demand reached 670,000 wafers in 2025, heading toward 1 million in 2026—while TSMC capacity is approximately 75,000-80,000 wafers per month. NVIDIA has locked down 50%+ of total CoWoS capacity through 2027, leaving AMD, Google, custom ASIC designers, and others in a “fierce bidding war” for remaining allocation. Lead times for AI servers exceed 50 weeks.
Aletheia Capital’s Warren Lau forecasts TSMC will more than double its advanced capacity (<5nm) from FY25E to FY28E, with capex reaching $60-65 billion annually by FY27E—up from $42 billion in FY25E. Even this unprecedented investment may not fully address demand from heterogeneous chiplet architectures. Lau explicitly cites “assembly technology and capacity (CoWoS, CoPoS and SoIC)” as critical constraints. This supply-demand imbalance is precisely what creates the opening for Intel’s EMIB—not as a CoWoS replacement, but as necessary overflow capacity for hyperscaler ASICs that can’t secure TSMC allocation.
TSMC pricing power: Annual ASP increases accelerated from essentially flat (2004-2019) to 15.9% annually since 2019. Gross profit per wafer increased 3.3x through 2025. 2nm wafers command 50%+ premiums over 3nm, potentially exceeding $30,000 per wafer. CoWoS packaging faces 10-20% price increases over the next two years. Customers accept these increases because alternatives haven’t existed—diversification restores negotiating leverage.
Taiwan geopolitical risk: Taiwan produces 90% of the world’s most advanced semiconductors. Academic analysis suggests Taiwan’s supply chain is “particularly vulnerable to a quarantine initiated before 2027.” While the “Silicon Shield” thesis suggests Taiwan’s chip dominance deters military action, hyperscalers are unwilling to bet their AI infrastructure on geopolitical stability.
US manufacturing preference: The CHIPS Act’s $52.7 billion in funding explicitly targets domestic advanced packaging capacity. Commerce Secretary Gina Raimondo identified packaging as a “critical vulnerability.” All major hyperscalers have made public commitments to US supply chains—Apple’s $600 billion US investment, AWS confirming TSMC Arizona adoption, Microsoft explicitly citing “US-based chip supply chain” as rationale for Intel engagement.
For Intel, currently trading around $39-41, this represents a high-risk/high-reward turnaround play. The stock is up ~80% in 2025—one of its best years since 1996—but analyst consensus remains Hold with wide price target dispersion ($20-$52). Sum-of-parts analysis suggests $34-40 fair value in the base case, with 60%+ upside potential if 14A executes and major customers materialize.
Bull case ($45-52): 14A achieves yield targets with High-NA EUV, multiple hyperscaler customers commit to EMIB+14A bundles, NVIDIA Feynman packaging deal materializes at the reported ~25% share, advanced packaging revenue reaches $5-10B annually by 2028. The DigiTimes report on Feynman significantly strengthens this scenario. Probability: 30-35%.
Base case ($32-40): Internal products succeed, 1-2 external customers (Microsoft, Amazon) represent meaningful but limited revenue. Packaging gains traction while logic foundry remains subscale. Probability: 40-45%.
Bear case ($20-25): 18A yields don’t improve, customers don’t materialize, 14A cancelled. Foundry wound down as commercial failure. Probability: 25-30%.
For TSMC, Intel competition is manageable, not existential. Even if hyperscalers diversify 10-20% of advanced packaging volume to Intel, that represents ~$2-4 billion in annual revenue impact—roughly 2-3% of TSMC’s total. CoWoS capacity remains fully booked through 2026-2027 regardless of Intel’s progress.
Interestingly, DigiTimes’ January 28 report suggests TSMC may view partial order diversion as “benefits far outweighing costs” for three strategic reasons: (1) reduces antitrust and monopoly scrutiny, (2) relieves political pressure from the Trump administration, and (3) only “non-core” orders migrate—TSMC retains high-margin flagship chips while potentially gaining pricing leverage when customers experience Intel’s learning curve. As one supply chain source told DigiTimes: “Perhaps customers who try other foundries will appreciate TSMC’s value more.” TSMC remains the preferred AI semiconductor exposure.
For Broadcom, risk from Intel packaging wins is minimal. Broadcom’s value lies in chip design expertise that hyperscalers lack internally—even if Google uses Intel EMIB for TPU v9 packaging, Broadcom’s design role for TPU silicon likely continues. The $73 billion AI order backlog provides 2+ years visibility.
Timeline to watch: Material foundry revenue ($1B+ quarterly) likely won’t appear until 2028 earnings. Near-term catalysts include Q4 2025/Q1 2026 customer announcements, 18A yield trajectory updates, and any “anchor customer” wins beyond Microsoft and Amazon. The critical milestone is major external customer announcement by mid-2026—without it, Intel has signaled 14A and beyond may be cancelled.
Intel’s EMIB packaging technology represents a genuine technical alternative to TSMC’s CoWoS—with real advantages in power efficiency, thermal performance, cost structure, and available US-based capacity. The hyperscaler motivation to diversify is equally genuine, driven by CoWoS capacity constraints, TSMC pricing power, Taiwan geopolitical risk, and US manufacturing preferences.
The customer pipeline is now more concrete than skeptics assumed. NVIDIA’s partnership is confirmed and expanding—the just-reported Feynman GPU exploration (with ~25% packaging share potentially going to Intel EMIB) would represent the first significant non-TSMC packaging for NVIDIA’s flagship GPUs. Google TPU engagement appears substantive for v8e/v9. Intel’s Q4 2025 earnings confirmed advanced packaging as the “brightest spot” for IFS, with external engagements crossing from hundreds of millions into billions of dollars.
This is still a 2027+ story requiring Intel to execute multiple first-of-kind technologies simultaneously—but the thesis has strengthened materially in recent weeks. 18A yields at ~60% with 7% monthly improvement, 40k→100k wafer/month ramp targets, and now potential NVIDIA Feynman validation all suggest the turnaround may be ahead of bearish consensus.
The investment opportunity exists for those with high risk tolerance and a 2-3 year horizon. Intel’s bundled 14A+EMIB strategy addresses a real market need, CHIPS Act support reduces existential risk, and momentum is building. But investors should size positions accordingly: execution must continue, substrate bottlenecks need resolution, and 14A CapEx remains gated on customer commitments. The most useful approach is milestone-based accumulation—adding exposure as Intel demonstrates continued yield improvements, converts packaging engagements to logic foundry deals, and delivers on the Feynman and hyperscaler opportunities now emerging.
Subscribe to make sure you don’t miss it.
If you found this analysis valuable, please share it—it helps more than you know. And if you haven’t subscribed yet, now’s the time. BEP Research will be moving to paid soon in the coming weeks. I’m committed to delivering institutional-quality analysis on AI infrastructure that you won’t find anywhere else.
DigiTimes: NVIDIA 2028年釋單英特爾代工—三層面解讀台積電戰略思維 (January 28, 2026) — Original Chinese report on NVIDIA Feynman, Apple M-series, and TSMC strategic response
DigiTimes: NVIDIA Exploring Intel Collaboration for Feynman GPUs (January 27, 2026)
Tom’s Hardware: Why NVIDIA’s $5B Partnership Is About Intel’s Packaging
CNBC: Nvidia Takes $5 Billion Stake in Intel Under September Agreement
TrendForce: Intel Gains Momentum—18A Eyes Apple, EMIB Reportedly Tapped for Google-MediaTek TPUs
FundaAI: INTC 4Q25 Preview—Supply Bottlenecks Drive ASP Uplift; 18A Yields and Restructuring Fuel Margin Expansion (January 2026)
Alex_Intel_: The Definitive Edition—Analysis of Every Single Intel Fab Across the US, Ireland, Israel, and Malaysia (January 2026)
Citrini Research: Intel Q4 2025 Earnings Analysis (January 2026)
Warren Lau, Aletheia Capital: TSMC capacity and capex forecasts (January 2026)
Ben Pouladian is a Los Angeles-based tech investor and entrepreneur focused on AI infrastructure, semiconductors, and the power systems enabling the next generation of compute. He was co-founder of Deco Lighting (2005–2019), where he helped build one of the leading commercial LED lighting manufacturers in North America. Ben holds an electrical engineering degree from UC San Diego, where he worked in Professor Fainman’s ultrafast nanoscale optics lab on silicon photonics and micro-ring resonators, and interned at Cymer, the company that manufactures the EUV light sources for ASML’s lithography systems.
He currently serves as Chairman of the Leadership Board at Terasaki Institute for Biomedical Innovation and is a YPO member. His investment research focuses on AI datacenter infrastructure, GPU computing, and the semiconductor supply chain. Long-term NVIDIA investor since 2016.
Follow on Twitter/X: @benitoz | More at benpouladian.com
Disclosure: The author holds positions in NVIDIA, Intel, and related semiconductor investments. This is not investment advice.
Originally published on BEP Research on Substack. Subscribe for more.
Leave a Reply