Ben Pouladian's Blog

Happy New Year, and thank you to all my new subscribers! I hope 2026 brings you clarity in your investments and curiosity in your research. With CES kicking off this week, the tech world is buzzing—but I wanted to step back from the product announcements and dig into something more fundamental: the manufacturing constraints that will determine who actually ships AI chips at scale.

The timing feels right. This week brought reports that Broadcom struggled to secure additional CoWoS capacity from TSMC for Google’s TPU production—a concrete example of exactly the bottleneck this piece explores. When the world’s most sophisticated chip designers can’t get packaging capacity, you know the constraint is real.

This piece is personal for me. Back in college at UC San Diego, I did an internship at Cymer—the company that makes the EUV light sources powering ASML’s lithography systems. Watching those engineers push the boundaries of extreme ultraviolet technology gave me an early appreciation for just how hard semiconductor manufacturing really is. That experience shaped how I think about the industry today.

I hope you enjoy this deep dive. Let’s get into it.

When I was working in Professor Fainman’s ultrafast nanoscale optics lab at UC San Diego, we spent countless hours wrestling with electrostatic effects at the nanometer scale. The challenge of controlling light in micro-ring resonators taught me that physics doesn’t negotiate—once you hit fundamental limits, no amount of engineering cleverness buys you more runway. You need an architectural change.

TSMC just made that architectural change with 2nm Gate-All-Around (GAA) transistors—the most significant transistor structure overhaul since FinFETs arrived in 2011. The semiconductor press is rightfully covering this milestone. Equipment intensity increases 30-50% per wafer start, driving a multi-year capex cycle that SEMI projects will reach $156 billion by 2027.

But here’s what most coverage misses: the real bottleneck isn’t transistor density anymore. It’s advanced packaging.

NVIDIA commands an estimated 70%+ of TSMC’s CoWoS-L capacity. Broadcom’s hyperscaler empire—Google, Apple, Meta, Anthropic, OpenAI, ByteDance—fights for the rest. You can have the most advanced 2nm compute dies in the world, but if you can’t package them with HBM memory on a CoWoS interposer, they’re just expensive silicon sitting in inventory.

The GAA transition and the CoWoS wars are two sides of the same coin. Understanding both is essential for positioning in this cycle.

Let’s dig in.

Part I: The GAA Transition—Why It Matters for Equipment Investors

The Physics: Why FinFETs Hit the Wall

For anyone who’s studied device physics, the FinFET scaling problem was predictable. FinFETs gave us tri-gate control—wrapping the gate around three sides of a vertical silicon fin. At 7nm and 5nm, this worked beautifully. But at sub-5nm gate lengths, the math breaks down catastrophically.

The culprit is drain-induced barrier lowering (DIBL). As the channel shrinks, the drain’s electric field penetrates deeper into the channel region, lowering the potential barrier that keeps current from flowing in the “off” state. Below 5nm, DIBL exceeds 100mV/V—which means your transistor leaks current like a sieve when it’s supposed to be off. Subthreshold swing degrades from the ideal 60mV/decade to 70-90mV/decade.

I remember similar scaling walls in photonics—there’s a point where you’re fighting thermodynamics, not engineering problems. At Deco Lighting, we eventually learned that hitting physical limits meant rethinking the architecture, not just optimizing the existing approach.

GAA nanosheets solve this by wrapping the gate around all four sides of horizontally stacked silicon ribbons. TCAD simulations show 65-83% DIBL reduction versus equivalent FinFET dimensions. That’s not incremental—that’s a step-function improvement in electrostatic control.

FinFET vs GAA nanosheet cross-section comparison diagram

The Nanosheet Stack Architecture

TSMC’s N2 implementation stacks 3-4 silicon nanosheets, each approximately 5nm thick and 10-50nm wide, with 7-15nm spacing between sheets. The “natural length” governing electrostatic integrity is roughly 30% smaller for GAA compared to tri-gate structures—which is why this architecture enables continued scaling.

What excites me most from a design flexibility standpoint is TSMC’s “NanoFlex” technology. Variable nanosheet widths on the same chip break the quantized width limitation that constrained FinFET designs. Narrow sheets for low-power cores, wide sheets for high-performance—on the same die. That’s genuine architectural freedom.

The roadmap beyond nanosheets is clear: forksheets (expected ~2028) introduce dielectric walls between n/p devices for tighter spacing, then CFETs (expected ~2032) vertically stack nMOS directly on pMOS.

Process Complexity Explosion: The Equipment Investment Thesis

This is where the equipment investment thesis crystallizes. The GAA transition introduces 4-5 entirely new process modules that extend fabrication sequences by roughly 20%. Every one of these steps requires specialized equipment.

Si/SiGe Superlattice Epitaxy: Building alternating layers of sacrificial silicon-germanium and silicon channel layers with nanometer-precision thickness control. This is Applied Materials’ sweet spot with the Centura Prime Epi platform.

Inner Spacer Formation: The most complex new module. After lateral isotropic etching recesses the SiGe layers, conformal LPCVD deposits a dielectric, followed by precise etch-back to create 9-10nm inner spacers. Moon-shaped spacer profiles risk TDDB reliability failures.

Nanosheet Release Etch: Here’s where Lam Research earns its premium valuation. Selectively removing SiGe while preserving silicon channels requires >100:1 selectivity. Lam commands an estimated 80% market share in sub-5nm selective etch, according to industry analysts. Their Selis and Prevos platforms are essentially irreplaceable.

Replacement Metal Gate: Depositing high-k dielectric and work function metals into spaces between suspended sheets pushes ALD to its limits. Applied Materials’ IMS platform achieves approximately 1.5 angstroms better equivalent oxide thickness versus competitors.

Metrology Explosion: KLA reports GAA drives 30% more high-end film metrology layers and 50% more critical inspection layers versus FinFET.

Equipment Intensity: The Numbers

Applied Materials quantifies it directly: equipment revenue per 100,000 wafer starts/month expands from approximately $6B to $7B with GAA + backside power delivery. That’s structural demand growth independent of unit volumes.

Part II: The Packaging Paradox—Why CoWoS Is the Real Constraint

Here’s the insight most semiconductor coverage misses: advanced packaging capacity—not transistor density—has become the critical constraint shaping AI chip leadership.

You can have the most advanced 2nm compute dies in the world. But if you can’t package them with HBM memory in a CoWoS interposer, they’re just expensive silicon sitting in inventory.

Why CoWoS Is So Hard

Let me break down why advanced packaging is such a bottleneck—this is the “primer” part that most coverage skips.

The Reticle Limit Problem: A single EUV exposure can only pattern an area of about 858mm² (the “reticle limit”). NVIDIA’s GB100 die is already at 814mm²—essentially maxed out. To build bigger systems, you must connect multiple dies together. That’s packaging.

The Interposer Challenge: CoWoS places multiple chips on a silicon or organic interposer that provides ultra-dense wiring between them. The original CoWoS-S uses a monolithic silicon interposer—but silicon becomes brittle and warps beyond ~3.3x reticle size (~2,700mm²). That’s why TSMC developed CoWoS-L.

The CTE Mismatch Nightmare: Different materials expand at different rates when heated. When you’re bonding GPU dies (silicon), LSI bridges (silicon), organic interposer (polymer), and substrate (laminate) together—then running the system at 1,400W—thermal expansion mismatches cause warping, cracking, and connection failures. This is what delayed Blackwell in Q3-Q4 2024.

The HBM Integration Complexity: Each HBM3e stack contains 8-12 DRAM dies with thousands of through-silicon vias (TSVs), bonded with 20-30 micron pitch micro-bumps. HBM4 (expected 2026) pushes this to 10 micron pitch with 2,048-bit interfaces. The yield math is punishing—one bad connection in thousands kills the package.

The Capacity Crunch: TSMC Is Doubling Every Year and Still Can’t Keep Up

TSMC CEO C.C. Wei confirmed: “Supply continues to be very tight, all the way to probably 2025, and I hope it can be eased in 2026.”

Despite doubling capacity in both 2024 and 2025, demand continues to outpace supply.

The pricing tells the story: advanced packaging ASP increases of 10-20% annually versus logic wafer increases of just 5%. TSMC’s packaging business now represents an estimated 7-9% of revenue with margins approaching company average (~53% gross).

The Capacity War: Who Gets the Wafers?

Morgan Stanley’s detailed analysis reveals the allocation hierarchy:

NVIDIA’s estimated 70%+ share of CoWoS-L specifically (the variant needed for Blackwell’s dual-die design) creates structural advantage—but also concentration risk if TSMC decides to diversify.

Part III: The Players—NVIDIA, Broadcom, and the Hyperscaler Shift

NVIDIA: Skipping N2 Entirely for A16’s Backside Power

NVIDIA’s process roadmap reveals a strategic bet on power delivery over raw density. Rather than adopting TSMC’s baseline N2, NVIDIA is reportedly the first—and initially only—customer for A16, TSMC’s 1.6nm node featuring Super Power Rail backside power delivery.

This makes sense when you understand the power problem. Blackwell Ultra operates at 1,400W TDP. Rubin targets an expected 2,300W. At these levels, frontside power delivery creates intolerable IR drop. A16’s Super Power Rail moves power delivery to the wafer backside.

Broadcom: The Custom Silicon Empire

While everyone watches NVIDIA, Broadcom has quietly built an estimated $60-90 billion serviceable addressable market in custom AI accelerators. CEO Hock Tan projects this from just three hyperscaler customers initially, with more now in development.

Broadcom commands an estimated 70% market share in custom AI accelerators, with FY2024 AI revenue reaching $12.2 billion (up 220% YoY).

The hyperscaler shift is real. Every major AI company is hedging NVIDIA dependency with custom silicon—and Broadcom is their design partner of choice.

Part IV: Equipment Beneficiaries—Who Captures the GAA + CoWoS Premium?

ASML: EUV Monopoly Extends

Important clarification: High-NA EUV (0.55 NA) is not strictly required for 2nm. Foundries can use standard 0.33 NA EUV with multi-patterning. High-NA becomes critical for sub-2nm (1.5nm, 1.4nm).

EUV layer counts continue expanding: approximately 15 layers at 5nm → 25+ layers at 2nm → 30+ layers at 1.4nm. Each layer drives system sales and service revenue.

High-NA economics: €350-380M per EXE:5000/5200 system. Current valuation at 38-40x trailing P/E prices in monopoly economics, but China normalization (36% → ~20% of revenue) creates headwinds.

Applied Materials: GAA Revenue Doubling

GAA revenue trajectory: approximately $2.5B (FY2024) → ~$4.5B (FY2025). The Centura Prime Epi deposits nanosheets; Producer Selectra handles selective etch; IMS integrates ALD/thermal/plasma for gate stacks.

At 18-19x trailing P/E (14x forward), Applied Materials trades at material discounts to peers despite GAA share gains. China exposure (30%) weighs on sentiment.

Lam Research: Selective Etch Monopoly

Lam Research occupies the most defensible position. The nanosheet release etch requires the estimated ~80% market share in sub-5nm etch that Lam commands. Selis, Prevos, and new Akara platforms are irreplaceable.

Q4 FY2025: $5.17B revenue, 50.3% gross margin (multi-year high), 34.4% operating margin. Valuation at ~33x trailing P/E (vs 10-year average 18.6x) reflects irreplaceability premium.

KLA: Metrology Complexity Explosion

GAA drives 30% more film metrology layers and 50% more inspection layers. The eSL10 e-beam achieves 1-3nm defect sensitivity for buried GAA structures.

At ~29x trailing P/E with approximately 62% gross margins (industry-leading), KLA offers more reasonable valuation than Lam Research with similar structural tailwinds.

Tokyo Electron: Coater/Developer Dominance

Tokyo Electron’s estimated 92% coater/developer market share makes it essential for any EUV-based process. At ~23x P/E post-correction (down 30%+ from April 2024 peak), Tokyo Electron offers attractively valued exposure.

Valuation Snapshot

Part V: The TSMC Roadmap—Tying It Together

Key Risks

China Exposure: December 2024 export controls imposed restrictions on 24 equipment types. Revenue impacts: ASML China dropped from 41% → 27%; Applied Materials from 45% → 25%; Lam Research maintains 34-42% exposure (”significant risk factor”).

Customer Concentration: TSMC’s $38-42B capex represents ~30-35% of global WFE. Samsung foundry collapsed to 7.7% share (Q1 2025); Intel Ohio fab delayed to 2030-2031. Equipment demand increasingly depends on TSMC execution.

AI Demand Sustainability: DeepSeek’s efficient model ($6M, 2 months) raised questions about capex intensity. If AI infrastructure spending moderates, leading-edge demand could disappoint.

CoWoS Yield Risk: Blackwell’s Q3-Q4 2024 delays stemmed from CoWoS-L yield issues (CTE mismatch). Future architectures face similar risks as package complexity increases.

The Bottom Line

The FinFET→GAA transition represents a generational inflection in semiconductor manufacturing complexity. Equipment intensity increases of 30-50% per wafer start create structural demand growth independent of unit volumes.

But the real insight is this: CoWoS capacity, not transistor density, determines who wins in AI semiconductors.

NVIDIA’s estimated 70%+ CoWoS-L allocation creates structural advantage. Broadcom’s hyperscaler empire—now including Google, Apple, Meta, Anthropic, OpenAI, and ByteDance—captures the rest. The GAA transition matters for equipment investors, but the advanced packaging fabs being constructed across Taiwan will determine who can actually ship AI chips at scale.

For equipment investors:

• Lam Research: Most defensible GAA exposure through selective etch monopoly, but premium valuation requires conviction

• Applied Materials: Attractively valued with GAA revenue doubling ($2.5B→$4.5B), potential catch-up candidate

• KLA: 50% inspection layer increase with industry-leading margins, more reasonable valuation

• ASML: EUV monopolist facing China normalization headwinds, but indispensable for advanced nodes

• Tokyo Electron: Post-correction value with 92% coater/developer dominance

Position sizing should reflect elevated valuations and China concentration. But the structural tailwind from GAA complexity and CoWoS scarcity remains intact regardless of near-term cyclical concerns.

The physics always wins. And the physics of both GAA transistors and advanced packaging demand more equipment—and more packaging capacity—than any previous generation.